As is known, some integrated devices are provided with a test structure, which allows a testing operation on particular portions of the integrated device.
To this end, the test structure is provided with a third-level detecting device, which has the function of simplifying switching of the integrated device from a standard operative condition to a test operative condition. In addition, the third-level detecting device has the function of preventing as far as possible accidental activation of the test operative condition when the integrated device is in the standard operative condition.
In general, the test operative condition is activated by taking a specific pin of the integrated device to a higher than a standard voltage value, which is recognized by the integrated device as a high logic level signal.
An integrated device with operativity test, for example a non-volatile memory of a known type, is shown in FIG. 1 and is described hereinafter.
In FIG. 1, a memory 1 comprises an input stage 2 for addressing lines or columns of a memory array (not shown), belonging to the memory 1, and a third-level detecting stage 3. The input stage 2 and the third level detecting stage 3 have respective input terminals 2a, 3a, both connected to a pad 5. The input stage 2 further has an output terminal 2b supplying an address signal ADD<N> for the memory array, whereas the third-level detecting stage 3 has a first and a second output terminal 3b, 3crespectively supplying a third-level signal TL and an inverted third-level signal TL_N.
The input stage 2 comprises a first and a second inverter 6 and 7 of MOS type. The first inverter 6 comprises a pull-up transistor 8 of PMOS type, and a pull-down transistor 9 of NMOS type, which are connected between a supply line 10 set to a voltage Vdd, and a ground line 11. In detail, the pull-up transistor 8 has a source terminal connected to the supply line 10, a drain terminal connected to a first node 12, and a gate terminal connected to the input terminal 2a of the input stage 2. The pull-down transistor 9 has a gate terminal connected to the input terminal 2a of the input stage 2, a source terminal connected to the ground line 11, and a drain terminal connected to the first node 12; the inverter 7 has an input connected to the first node 12, and an output which defines the output terminal 2b of the input stage 2.
The third level detecting stage 3 comprises three PMOS transistors 15 connected as diodes, an NMOS transistor 18 of natural type, and a third, a fourth and a fifth inverter 19, 20 and 21.
The PMOS transistors 15 are connected to one another in series, between the input terminal 3a of the third-level detecting stage 3, and a second, intermediate node 22.
The NMOS transistor 18 has a source terminal connected to the ground line 11, and gate and drain terminals connected to one another and to the second node 22.
The third, fourth and fifth inverters 19, 20 and 21 are cascade connected together between the second node 22 and the second output terminal 3c of the third-level detecting stage 3. The output of the inverter 20 defines the first output terminal 3b of the third-level detecting stage 3.
In the standard operative condition of the memory 1, when the address signal ADD<N> is to be generated, the pad 5 is supplied with an input signal S at a high logic level, the value of which (for example of 3 V) is lower than the voltage necessary for switching on the PMOS transistors 15 and the NMOS transistor 18 (the latter being the sum of the respective threshold voltages). In this condition, any leakage currents flow through the NMOS transistor 18; thus, the second node 22 is grounded; the third-level signal TL is at low logic level, and the signal TL_N is at high logic level.
When testing is to be carried out, a test voltage VTL, of for example 12 V, and higher than the voltage of the high logic level of the input signal S, is applied to the pad 5; the PMOS transistors 15 and the NMOS transistor 18 therefore switch on; consequently, the voltage at the second node 22 exceeds the trip level of the third inverter 19, and the signals TL and TL_N switch respectively to the high and low logic levels.
When the signal TL is at high logic level, the memory 1 switches from the standard operative condition to the test operative condition, and carries out the planned test operations, not described hereinafter since they are not the subject of the present invention.
The integrated devices of the above-described type have the disadvantage that when the memory 1 enters the test operative condition, a high potential difference, higher than in the standard operative condition, is present between the gate terminal and the source terminal of the pull-down transistor 9; consequently, in the test operative condition, the pull-down transistor 9 is subjected to a high stress, which can damage the pull-down transistor 9. This applies in particular in the case of integrated devices designed for operating at a low voltage, where the potential difference existing between the gate and the source terminals of the pull-down transistor 9 can exceed the dielectric rigidity of the gate oxide of the pull-down transistor 9.